AN APPROACH TO DEVELOP INTELLIGENT DIGITAL TEST SYSTEMS

A new test generation method is developed for digital systems on the basis of alternative graphs. Tests are generated using symbolic signal values and are organized in the compact way - in form of symbolic test programs and data arrays. A new architecture is pro- posed for test systems which is suited for on-line generating deterministic test patterns in algorithmic way. Special features are implemented in test generator and tester to support event driven testing, which makes it possible to test dynamically devices that work at higher clock rates than the tester does

ALGORITHMS OF FUNCTIONAL LEVEL TESTABILITY ANALYSIS FOR DIGITAL CIRCUITS

A general approach is proposed for calculating controllabilities and observabilities of signals in sequential and combinational circuits at the functional level. The methods and algorithms are based on alternative graphs which are an extension of binary decision diagrams. The algorithms are general and can be easily adjusted for calculation of different testability measures.

Mixed-level identification of fault redundancy in microprocessors

A new high-level implementation independent functional fault model for control faults in microprocessors is introduced. The fault model is based on the instruction set, and is specified as a set of data constraints to be satisfied by test data generation. We show that the high-level test, which satisfies these data constraints, will be sufficient to guarantee the detection of all non-redundant low level faults. The paper proposes a simple and fast simulation based method of generating test data, which satisfy the constraints prescribed by the proposed fault model, and a method of evaluating the high-level control fault coverage for the proposed fault model and for the given test. A method is presented for identification of the high-level redundant faults, and it is shown that a test, which provides 100% coverage of non-redundant high-level faults, will also guarantee 100% non-redundant SAF coverage, whereas all gate-level SAF not covered by the test are identified as redundant. Experimental results of test generation for the execution part of a microprocessor support the results presented in the paper.Comment: 2019 IEEE Latin American Test Symposium (LATS

Remote boundary-scan testing through micro-webservers

The IEEE 1149.1 standard test access port and boundary-scan architecture [1] was approved in1990 in response to the need for coping with shrinking sizes due to advanced packaging andmounting technologies, and also with the increasing complexity of modern microelectronicdevices. Boundary-scan test (BST) was quickly adopted by all industry sectors, including testequipment manufacturers, CAD tool providers, and microcircuit designers and manufacturers.Many tools and integrated solutions are now available on the market to support BST, but theyare essentially dedicated to production test environments. The work presented in this documentaddresses the development of a network of low-cost distributed BST controllers, based onmicro-webserver boards

Learning digital test and diagnostics via Internet

An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access to the hardware equipments, which can be used in the classroom, for learning at home, in laboratory research and training, or for carrying out testing of students during exams. The tools support university courses on digital electronics, computer hardware, testing and design for testability to learn by hands-on exercises how to design digital systems, how to make them testable, how to build self-testing systems, how to generate test patterns, how to analyze the quality of tests, and how to localize faults in hardware. The tasks chosen for hands-on training represent simultaneously research problems, which allow to fostering in students critical thinking, problem solving skills and creativity

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics